Duplicated register file design for embedded simultaneous multithreading microprocessor

Zang Chengjie, Shigeki Imai, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In modern microprocessors, the access time of register file becomes a critical part in total delay. Instruction level or thread level parallelism improves Instructions Per. Cycle (IPC) by executing multiple instructions in one cycle. Such multiple instructions need to read or write data from/to register files simultaneously. To satisfy that, register file with sufficient ports should be designed. However, the area and access time of register file with large ports will increase sharply. Duplicated Register File (DupRF) architecture can reduce access time by distributing read ports. In this paper, we propose a new kind of DupRF architecture for embedded Simultaneous Multithreading (SMT) microprocessor and estimate the effect with respect to the area and access time. Especially, we measure the product of area and access time as computation cost. For a SMT microprocessor with 6 threads, 64-bit data-width and 6 function units, a 3-duplicate register file architecture can reduce access time by 12.61% with a slight increase of computation cost by 3.35% compared with the central register file architecture.

Original languageEnglish
Title of host publicationASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Pages160-163
Number of pages4
Volume1
Publication statusPublished - 2005
EventASICON 2005: 2005 6th International Conference on ASIC - Shanghai
Duration: 2005 Oct 242005 Oct 27

Other

OtherASICON 2005: 2005 6th International Conference on ASIC
CityShanghai
Period05/10/2405/10/27

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Microprocessor chips
Costs

Keywords

  • Access time
  • Computation cost
  • Duplicated Register File (DupRF)
  • Simultaneous multithreading

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chengjie, Z., Imai, S., & Kimura, S. (2005). Duplicated register file design for embedded simultaneous multithreading microprocessor. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings (Vol. 1, pp. 160-163). [1611275]

Duplicated register file design for embedded simultaneous multithreading microprocessor. / Chengjie, Zang; Imai, Shigeki; Kimura, Shinji.

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1 2005. p. 160-163 1611275.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chengjie, Z, Imai, S & Kimura, S 2005, Duplicated register file design for embedded simultaneous multithreading microprocessor. in ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. vol. 1, 1611275, pp. 160-163, ASICON 2005: 2005 6th International Conference on ASIC, Shanghai, 05/10/24.
Chengjie Z, Imai S, Kimura S. Duplicated register file design for embedded simultaneous multithreading microprocessor. In ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1. 2005. p. 160-163. 1611275
Chengjie, Zang ; Imai, Shigeki ; Kimura, Shinji. / Duplicated register file design for embedded simultaneous multithreading microprocessor. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings. Vol. 1 2005. pp. 160-163
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