Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently a demand for high-speed wireless network service on mobile devices is rapidly increasing. Error correcting codes are used to enhance network communication quality. Particularly, LDPC (Low Density Parity Check) codes show high throughput and achieve information rates very close to the Shannon limit. In this paper, we propose a dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. Our proposed decoder deals with multi-rate codes by introducing a multi-rate compatible 1st-2nd minimum searching unit. The proposed decoder shows the better throughput over the wide range of S/N ratio compared to conventional rate-fixed LDPC decoders.

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages705-708
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 2008 Nov 302008 Dec 3

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period08/11/3008/12/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 705-708). [4746121] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746121