Edge effect prediction in real MOS insulator using test chips

Jiro Yugami, Atsushi Hiraiwa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.

Original languageEnglish
Title of host publicationTest Structures
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages17-22
Number of pages6
ISBN (Print)0879425881
Publication statusPublished - 1991
EventProceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn
Duration: 1991 Mar 181991 Mar 20

Other

OtherProceedings of the 1991 International Conference on Microelectronic Test Structures
CityKyoto, Jpn
Period91/3/1891/3/20

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Yugami, J., & Hiraiwa, A. (1991). Edge effect prediction in real MOS insulator using test chips. In Test Structures (pp. 17-22). Publ by IEEE.