Abstract
The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.
| Original language | English |
|---|---|
| Title of host publication | Test Structures |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | Publ by IEEE |
| Pages | 17-22 |
| Number of pages | 6 |
| ISBN (Print) | 0879425881 |
| Publication status | Published - 1991 |
| Event | Proceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn Duration: 1991 Mar 18 → 1991 Mar 20 |
Other
| Other | Proceedings of the 1991 International Conference on Microelectronic Test Structures |
|---|---|
| City | Kyoto, Jpn |
| Period | 91/3/18 → 91/3/20 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Edge effect prediction in real MOS insulator using test chips. / Yugami, Jiro; Hiraiwa, Atsushi.
Test Structures. Piscataway, NJ, United States : Publ by IEEE, 1991. p. 17-22.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Edge effect prediction in real MOS insulator using test chips
AU - Yugami, Jiro
AU - Hiraiwa, Atsushi
PY - 1991
Y1 - 1991
N2 - The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.
AB - The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.
UR - http://www.scopus.com/inward/record.url?scp=0026387061&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0026387061&partnerID=8YFLogxK
M3 - Conference contribution
SN - 0879425881
SP - 17
EP - 22
BT - Test Structures
PB - Publ by IEEE
CY - Piscataway, NJ, United States
ER -