Edge effect prediction in real MOS insulator using test chips

Jiro Yugami; Atsushi Hiraiwa

Edge effect prediction in real MOS insulator using test chips

Jiro Yugami, Atsushi Hiraiwa

Research Organization for Nano & Life Innovation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.

Original language	English
Title of host publication	Test Structures
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	17-22
Number of pages	6
ISBN (Print)	0879425881
Publication status	Published - 1991
Event	Proceedings of the 1991 International Conference on Microelectronic Test Structures - Kyoto, Jpn Duration: 1991 Mar 18 → 1991 Mar 20

Other

Other	Proceedings of the 1991 International Conference on Microelectronic Test Structures
City	Kyoto, Jpn
Period	91/3/18 → 91/3/20

ASJC Scopus subject areas

Engineering(all)

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Cite this

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title = "Edge effect prediction in real MOS insulator using test chips",

abstract = "The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.",

author = "Jiro Yugami and Atsushi Hiraiwa",

year = "1991",

language = "English",

isbn = "0879425881",

pages = "17--22",

booktitle = "Test Structures",

publisher = "Publ by IEEE",

note = "Proceedings of the 1991 International Conference on Microelectronic Test Structures ; Conference date: 18-03-1991 Through 20-03-1991",

}

TY - GEN

T1 - Edge effect prediction in real MOS insulator using test chips

AU - Yugami, Jiro

AU - Hiraiwa, Atsushi

PY - 1991

Y1 - 1991

N2 - The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.

AB - The authors propose an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs.

UR - http://www.scopus.com/inward/record.url?scp=0026387061&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026387061&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026387061

SN - 0879425881

SP - 17

EP - 22

BT - Test Structures

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - Proceedings of the 1991 International Conference on Microelectronic Test Structures

Y2 - 18 March 1991 through 20 March 1991

ER -