Ion milling is one of the promising methods for submicron pattern delineation in VLSI processes because of its potential for extremely small undercutting and high control. In gate electrode delineation using dry etching, degradation of the gate oxide must be avoided. The purpose of this work is to find those ion milling conditions where the gate oxide breakdown voltage is not degraded. Polysilicon gate MOS capacitors were fabricated delineating polysilicon films of various resistance by ion milling, and the breakdown voltage for the MOS capacitors was measured. The degradation was prevented when the polysilicon sheet resistance was lowered by annealing before ion milling.
|Title of host publication||Japanese Journal of Applied Physics, Part 2: Letters|
|Number of pages||2|
|Publication status||Published - 1983 Aug|
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