EFFECT OF PRE-ANNEALING IN PREVENTING GATE OXIDE BREAKDOWN VOLTAGE DEGRADATION INDUCED BY POLYSILICON GATE DELINEATION USING ION MILLING.

Noriyoshi Yamauchi, Toshiaki Yachi, Tsutomu Wada

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Ion milling is one of the promising methods for submicron pattern delineation in VLSI processes because of its potential for extremely small undercutting and high control. In gate electrode delineation using dry etching, degradation of the gate oxide must be avoided. The purpose of this work is to find those ion milling conditions where the gate oxide breakdown voltage is not degraded. Polysilicon gate MOS capacitors were fabricated delineating polysilicon films of various resistance by ion milling, and the breakdown voltage for the MOS capacitors was measured. The degradation was prevented when the polysilicon sheet resistance was lowered by annealing before ion milling.

Original languageEnglish
Title of host publicationJapanese Journal of Applied Physics, Part 2: Letters
Pages539-540
Number of pages2
Volume22
Edition8
Publication statusPublished - 1983 Aug
Externally publishedYes

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Yamauchi, N., Yachi, T., & Wada, T. (1983). EFFECT OF PRE-ANNEALING IN PREVENTING GATE OXIDE BREAKDOWN VOLTAGE DEGRADATION INDUCED BY POLYSILICON GATE DELINEATION USING ION MILLING. In Japanese Journal of Applied Physics, Part 2: Letters (8 ed., Vol. 22, pp. 539-540)