Effective capacitance for gate delay with RC loads

Zhang Cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance C eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages2795-2798
    Number of pages4
    DOIs
    Publication statusPublished - 2005
    EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    Duration: 2005 May 232005 May 26

    Other

    OtherIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
    CountryJapan
    CityKobe
    Period05/5/2305/5/26

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Huang, Z. C., Kurokawa, A., & Inoue, Y. (2005). Effective capacitance for gate delay with RC loads. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2795-2798). [1465207] https://doi.org/10.1109/ISCAS.2005.1465207