Effective post-BIST fault diagnosis for multiple faults

Hiroshi Takahashi; Shuhei Kadoyama; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato

doi:10.1109/DFT.2006.24

Effective post-BIST fault diagnosis for multiple faults

Hiroshi Takahashi^*, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

Original language	English
Title of host publication	Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	109-117
Number of pages	9
ISBN (Print)	076952706X, 9780769527062
DOIs	https://doi.org/10.1109/DFT.2006.24
Publication status	Published - 2006
Externally published	Yes
Event	2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, United States Duration: 2006 Oct 4 → 2006 Oct 6

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/Territory	United States
City	Arlington, VA
Period	06/10/4 → 06/10/6

ASJC Scopus subject areas

Engineering(all)

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10.1109/DFT.2006.24

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Takahashi, H., Kadoyama, S., Higami, Y., Takamatsu, Y., Yamazaki, K., Aikyo, T., & Sato, Y. (2006). Effective post-BIST fault diagnosis for multiple faults. In Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06 (pp. 109-117). [4030952] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2006.24

Effective post-BIST fault diagnosis for multiple faults. / Takahashi, Hiroshi; Kadoyama, Shuhei; Higami, Yoshinobu et al.

Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06. Institute of Electrical and Electronics Engineers Inc., 2006. p. 109-117 4030952 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takahashi, H, Kadoyama, S, Higami, Y, Takamatsu, Y, Yamazaki, K, Aikyo, T & Sato, Y 2006, Effective post-BIST fault diagnosis for multiple faults. in Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06., 4030952, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Institute of Electrical and Electronics Engineers Inc., pp. 109-117, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Arlington, VA, United States, 06/10/4. https://doi.org/10.1109/DFT.2006.24

Takahashi H, Kadoyama S, Higami Y, Takamatsu Y, Yamazaki K, Aikyo T et al. Effective post-BIST fault diagnosis for multiple faults. In Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06. Institute of Electrical and Electronics Engineers Inc. 2006. p. 109-117. 4030952. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFT.2006.24

Takahashi, Hiroshi ; Kadoyama, Shuhei ; Higami, Yoshinobu et al. / Effective post-BIST fault diagnosis for multiple faults. Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 109-117 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

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title = "Effective post-BIST fault diagnosis for multiple faults",

abstract = "With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.",

author = "Hiroshi Takahashi and Shuhei Kadoyama and Yoshinobu Higami and Yuzo Takamatsu and Koji Yamazaki and Takashi Aikyo and Yasuo Sato",

year = "2006",

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series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

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booktitle = "Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06",

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T1 - Effective post-BIST fault diagnosis for multiple faults

AU - Takahashi, Hiroshi

AU - Kadoyama, Shuhei

AU - Higami, Yoshinobu

AU - Takamatsu, Yuzo

AU - Yamazaki, Koji

AU - Aikyo, Takashi

AU - Sato, Yasuo

PY - 2006

Y1 - 2006

N2 - With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

AB - With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

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T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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ER -

Effective post-BIST fault diagnosis for multiple faults

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