Effective write-reduction method for MLC non-volatile memory

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly effective write-reduction method for a multi-level cell (MLC) non-volatile memory focusing on the write-reduction code (WRC) as the optimal bit-write reduction method. The WRC can be applied only to single-level cell non-volatile memory. The proposed method generates a cell-write reduction code based on the WRC; the cell has multiple bits as the holdable data. Our proposed method achieves a cell-write reduction by 31.6% compared to the conventional method.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 2017 Sep 25
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 2017 May 282017 May 31

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period17/5/2817/5/31

Fingerprint

Data storage equipment
Durability
Embedded systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tawada, M., Kimura, S., Yanagisawa, M., & Togawa, N. (2017). Effective write-reduction method for MLC non-volatile memory. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050699] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050699

Effective write-reduction method for MLC non-volatile memory. / Tawada, Masashi; Kimura, Shinji; Yanagisawa, Masao; Togawa, Nozomu.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050699.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tawada, M, Kimura, S, Yanagisawa, M & Togawa, N 2017, Effective write-reduction method for MLC non-volatile memory. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050699, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 17/5/28. https://doi.org/10.1109/ISCAS.2017.8050699
Tawada M, Kimura S, Yanagisawa M, Togawa N. Effective write-reduction method for MLC non-volatile memory. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050699 https://doi.org/10.1109/ISCAS.2017.8050699
Tawada, Masashi ; Kimura, Shinji ; Yanagisawa, Masao ; Togawa, Nozomu. / Effective write-reduction method for MLC non-volatile memory. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017.
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