Efficient algorithms for extracting pareto-optimal hardware configurations in DEPS framework

Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.

Original languageEnglish
Pages (from-to)133-142
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Volume5
DOIs
Publication statusPublished - 2012
Externally publishedYes

Keywords

  • Dynamic energy performance scaling
  • Embedded real-time system
  • Energy optimization

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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