Efficient capacitance extraction method for interconnects with dummy fills

Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    41 Citations (Scopus)

    Abstract

    The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

    Original languageEnglish
    Title of host publicationProceedings of the Custom Integrated Circuits Conference
    Pages485-488
    Number of pages4
    Publication statusPublished - 2004
    EventProceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States
    Duration: 2004 Oct 32004 Oct 6

    Other

    OtherProceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC
    CountryUnited States
    CityOrlando, FL
    Period04/10/304/10/6

    Fingerprint

    Capacitance
    Metals
    Chemical mechanical polishing
    Crosstalk
    Geometry

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Kurokawa, A., Kanamoto, T., Kasebe, A., Inoue, Y., & Masuda, H. (2004). Efficient capacitance extraction method for interconnects with dummy fills. In Proceedings of the Custom Integrated Circuits Conference (pp. 485-488)

    Efficient capacitance extraction method for interconnects with dummy fills. / Kurokawa, Atsushi; Kanamoto, Toshiki; Kasebe, Akira; Inoue, Yasuaki; Masuda, Hiroo.

    Proceedings of the Custom Integrated Circuits Conference. 2004. p. 485-488.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kurokawa, A, Kanamoto, T, Kasebe, A, Inoue, Y & Masuda, H 2004, Efficient capacitance extraction method for interconnects with dummy fills. in Proceedings of the Custom Integrated Circuits Conference. pp. 485-488, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, Orlando, FL, United States, 04/10/3.
    Kurokawa A, Kanamoto T, Kasebe A, Inoue Y, Masuda H. Efficient capacitance extraction method for interconnects with dummy fills. In Proceedings of the Custom Integrated Circuits Conference. 2004. p. 485-488
    Kurokawa, Atsushi ; Kanamoto, Toshiki ; Kasebe, Akira ; Inoue, Yasuaki ; Masuda, Hiroo. / Efficient capacitance extraction method for interconnects with dummy fills. Proceedings of the Custom Integrated Circuits Conference. 2004. pp. 485-488
    @inproceedings{d8c7e3e294724c44ba443a3be03a9fd6,
    title = "Efficient capacitance extraction method for interconnects with dummy fills",
    abstract = "The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30{\%}, whereas the error of the proposed method is less than about 10{\%} for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8{\%}.",
    author = "Atsushi Kurokawa and Toshiki Kanamoto and Akira Kasebe and Yasuaki Inoue and Hiroo Masuda",
    year = "2004",
    language = "English",
    pages = "485--488",
    booktitle = "Proceedings of the Custom Integrated Circuits Conference",

    }

    TY - GEN

    T1 - Efficient capacitance extraction method for interconnects with dummy fills

    AU - Kurokawa, Atsushi

    AU - Kanamoto, Toshiki

    AU - Kasebe, Akira

    AU - Inoue, Yasuaki

    AU - Masuda, Hiroo

    PY - 2004

    Y1 - 2004

    N2 - The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

    AB - The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

    UR - http://www.scopus.com/inward/record.url?scp=17044386168&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=17044386168&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:17044386168

    SP - 485

    EP - 488

    BT - Proceedings of the Custom Integrated Circuits Conference

    ER -