Efficient delay-matching bus routing by using multi-layers

Yang Tian, Ran Zhang, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently, signal propagation delay in a circuit implemented in VLSI or PCB becomes a very important problem due to the increasing clock frequency, where signal delay should be adjusted to meet the requirement of the delay time. The delay can be roughly estimated by the net length.While, due to the circuit complexity and the high density of integration, a single layer routing may not be enough for delay estimation. In current research, there's an algorithm for length matching bus routing for signal delay which has high efficiency. However, it doesn't put the high density of integration into consideration. The purpose of this paper is to route several nets by using multiple layers on a high density board to meet the signal delay requirement, even if there exist obstacles in the routing area. Previous research put focus on the single layer routing without considering the complexity and density of the board. In this paper, the complexity and density are taken into account. In our proposed algorithm, the routing area is divided into subareas to solve the problem efficiently, and nets can be assigned to the proper layers to avoid obstacles. After the net assignment, path generation is executed. Then, some optimizations are made to meet the signal delay for each net. Finally, the routing paths of nets which satisfy the delay constraint are determined. Experimental results using several examples show that our proposed method is highly effective and efficient.

Original languageEnglish
Title of host publication2014 International Conference on Electronics Packaging, ICEP 2014
PublisherIEEE Computer Society
Pages728-731
Number of pages4
ISBN (Print)9784904090107
DOIs
Publication statusPublished - 2014
Event2014 International Conference on Electronics Packaging, ICEP 2014 - Toyama
Duration: 2014 Apr 232014 Apr 25

Other

Other2014 International Conference on Electronics Packaging, ICEP 2014
CityToyama
Period14/4/2314/4/25

Fingerprint

Networks (circuits)
Polychlorinated Biphenyls
Polychlorinated biphenyls
Clocks
Time delay

Keywords

  • delay-matching
  • length-matching
  • obstacle
  • routing

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials

Cite this

Tian, Y., Zhang, R., & Watanabe, T. (2014). Efficient delay-matching bus routing by using multi-layers. In 2014 International Conference on Electronics Packaging, ICEP 2014 (pp. 728-731). [6826776] IEEE Computer Society. https://doi.org/10.1109/ICEP.2014.6826776

Efficient delay-matching bus routing by using multi-layers. / Tian, Yang; Zhang, Ran; Watanabe, Takahiro.

2014 International Conference on Electronics Packaging, ICEP 2014. IEEE Computer Society, 2014. p. 728-731 6826776.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tian, Y, Zhang, R & Watanabe, T 2014, Efficient delay-matching bus routing by using multi-layers. in 2014 International Conference on Electronics Packaging, ICEP 2014., 6826776, IEEE Computer Society, pp. 728-731, 2014 International Conference on Electronics Packaging, ICEP 2014, Toyama, 14/4/23. https://doi.org/10.1109/ICEP.2014.6826776
Tian Y, Zhang R, Watanabe T. Efficient delay-matching bus routing by using multi-layers. In 2014 International Conference on Electronics Packaging, ICEP 2014. IEEE Computer Society. 2014. p. 728-731. 6826776 https://doi.org/10.1109/ICEP.2014.6826776
Tian, Yang ; Zhang, Ran ; Watanabe, Takahiro. / Efficient delay-matching bus routing by using multi-layers. 2014 International Conference on Electronics Packaging, ICEP 2014. IEEE Computer Society, 2014. pp. 728-731
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