Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills

Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

    Original languageEnglish
    Pages (from-to)3471-3477
    Number of pages7
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE88-A
    Issue number12
    DOIs
    Publication statusPublished - 2005 Dec

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    Keywords

    • CMP
    • Dummy fill
    • Dummy metal
    • Interconnect capacitance

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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