Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC)

Achraf Ben Ahmed; Michael Meyer; Yuichi Okuyama; Abderazek Ben Abdallah

doi:10.1109/ICISCE.2015.52

Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC)

Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

Original language	English
Title of host publication	Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015
Editors	Shaozi Li, Ying Dai, Yun Cheng
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	202-206
Number of pages	5
ISBN (Electronic)	9781467368506
DOIs	https://doi.org/10.1109/ICISCE.2015.52
Publication status	Published - 2015 Jun 9
Externally published	Yes
Event	2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015 - Shanghai, China Duration: 2015 Apr 24 → 2015 Apr 26

Publication series

Name	Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015

Other

Other	2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015
Country/Territory	China
City	Shanghai
Period	15/4/24 → 15/4/26

Keywords

Architecture
Hybrid
Many-core Systems-on-Chip
Optical Network-on-Chip
Path Setting

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering
Computer Science(all)

Access to Document

10.1109/ICISCE.2015.52

Cite this

Ahmed, A. B., Meyer, M., Okuyama, Y., & Abdallah, A. B. (2015). Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). In S. Li, Y. Dai, & Y. Cheng (Eds.), Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015 (pp. 202-206). [7120592] (Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICISCE.2015.52

Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). / Ahmed, Achraf Ben; Meyer, Michael; Okuyama, Yuichi et al.

Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015. ed. / Shaozi Li; Ying Dai; Yun Cheng. Institute of Electrical and Electronics Engineers Inc., 2015. p. 202-206 7120592 (Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ahmed, AB, Meyer, M, Okuyama, Y & Abdallah, AB 2015, Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). in S Li, Y Dai & Y Cheng (eds), Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015., 7120592, Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015, Institute of Electrical and Electronics Engineers Inc., pp. 202-206, 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015, Shanghai, China, 15/4/24. https://doi.org/10.1109/ICISCE.2015.52

Ahmed AB, Meyer M, Okuyama Y, Abdallah AB. Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). In Li S, Dai Y, Cheng Y, editors, Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 202-206. 7120592. (Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015). doi: 10.1109/ICISCE.2015.52

Ahmed, Achraf Ben ; Meyer, Michael ; Okuyama, Yuichi et al. / Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC). Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015. editor / Shaozi Li ; Ying Dai ; Yun Cheng. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 202-206 (Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015).

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abstract = "Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.",

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N2 - Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

AB - Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

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Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC)

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