TY - GEN
T1 - Efficient router architecture, design and performance exploration for many-core hybrid photonic network-on-chip (2D-PHENIC)
AU - Ahmed, Achraf Ben
AU - Meyer, Michael
AU - Okuyama, Yuichi
AU - Abdallah, Abderazek Ben
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/6/9
Y1 - 2015/6/9
N2 - Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.
AB - Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.
KW - Architecture
KW - Hybrid
KW - Many-core Systems-on-Chip
KW - Optical Network-on-Chip
KW - Path Setting
UR - http://www.scopus.com/inward/record.url?scp=84938793937&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84938793937&partnerID=8YFLogxK
U2 - 10.1109/ICISCE.2015.52
DO - 10.1109/ICISCE.2015.52
M3 - Conference contribution
AN - SCOPUS:84938793937
T3 - Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015
SP - 202
EP - 206
BT - Proceedings - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015
A2 - Li, Shaozi
A2 - Dai, Ying
A2 - Cheng, Yun
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 2nd International Conference on Information Science and Control Engineering, ICISCE 2015
Y2 - 24 April 2015 through 26 April 2015
ER -