EM-X parallel computer: architecture and basic performance

Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Abstract

Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor communication on an execution pipeline with small and simple packets. It can create a packet in one cycle, and receive a packet from the network in the on-chip buffer without interruption. EM-X invokes threads on packet arrival, minimizing the overhead of thread switching. It can tolerate communication latency by using efficient multi-threading and optimizing packet flow of fine grain communication. EM-X also supports the synchronization of two operands, direct remote memory read/write operations and flexible packet scheduling with priority. This paper describes distinctive features of the EM-X architecture and reports the performance of small synthetic programs and larger more realistic programs.

Original languageEnglish
Pages14-23
Number of pages10
Publication statusPublished - 1995 Jan 1
EventProceedings of the 22nd Annual International Symposium on Computer Architecture - Santa Margherita Ligure, Italy
Duration: 1995 Jun 221995 Jun 24

Other

OtherProceedings of the 22nd Annual International Symposium on Computer Architecture
CitySanta Margherita Ligure, Italy
Period95/6/2295/6/24

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kodama, Y., Sakane, H., Sato, M., Yamana, H., Sakai, S., & Yamaguchi, Y. (1995). EM-X parallel computer: architecture and basic performance. 14-23. Paper presented at Proceedings of the 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, .