Embedded low-power dynamic TCAM architecture with transparently scheduled refresh

Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 μm 2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

    Original languageEnglish
    Pages (from-to)622-629
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE88-C
    Issue number4
    DOIs
    Publication statusPublished - 2005 Apr

    Fingerprint

    Static random access storage
    Macros
    Electric power utilization
    Capacitors
    Capacitance
    Power management

    Keywords

    • CMOS
    • Network
    • Refresh
    • Ternary CAM

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Noda, H., Inoue, K., Mattausch, H. J., Koide, T., Dosaka, K., Arimoto, K., ... Yoshihara, T. (2005). Embedded low-power dynamic TCAM architecture with transparently scheduled refresh. IEICE Transactions on Electronics, E88-C(4), 622-629. https://doi.org/10.1093/ietele/e88-c.4.622

    Embedded low-power dynamic TCAM architecture with transparently scheduled refresh. / Noda, Hideyuki; Inoue, Kazunari; Mattausch, Hans Jürgen; Koide, Tetsushi; Dosaka, Katsumi; Arimoto, Kazutami; Fujishima, Kazuyasu; Anami, Kenji; Yoshihara, Tsutomu.

    In: IEICE Transactions on Electronics, Vol. E88-C, No. 4, 04.2005, p. 622-629.

    Research output: Contribution to journalArticle

    Noda, H, Inoue, K, Mattausch, HJ, Koide, T, Dosaka, K, Arimoto, K, Fujishima, K, Anami, K & Yoshihara, T 2005, 'Embedded low-power dynamic TCAM architecture with transparently scheduled refresh', IEICE Transactions on Electronics, vol. E88-C, no. 4, pp. 622-629. https://doi.org/10.1093/ietele/e88-c.4.622
    Noda, Hideyuki ; Inoue, Kazunari ; Mattausch, Hans Jürgen ; Koide, Tetsushi ; Dosaka, Katsumi ; Arimoto, Kazutami ; Fujishima, Kazuyasu ; Anami, Kenji ; Yoshihara, Tsutomu. / Embedded low-power dynamic TCAM architecture with transparently scheduled refresh. In: IEICE Transactions on Electronics. 2005 ; Vol. E88-C, No. 4. pp. 622-629.
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