Abstract
Today in nanometer regime, approximate circuits have attracted much more attention due to the pursuit of low power consumption and high performance. Approximate multiplier is the key arithmetic function in many error-tolerant applications such as signal processing. In this paper, two approximate compressors based on input reordering logic have been proposed for the partial product reduction in the multiplication. A 2-bit reordering circuit is also designed for the proposed multiplier. Experimental results show that the proposed multiplier sacrifices only a small amount of precision (about 0.58%) to drastically reduce power, area, and delay up to (36.6%), (28.8%) and (20.1%) compared to accurate Wallace multiplier. The proposed multiplier achieves a high signal-to-noise ratio (over 50dB) when applied to an image processing algorithm.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 545-550 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781538654576 |
| DOIs | |
| Publication status | Published - 2019 Feb 22 |
| Event | 2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of Duration: 2018 Oct 28 → 2018 Oct 31 |
Publication series
| Name | IEEE Region 10 Annual International Conference, Proceedings/TENCON |
|---|---|
| Volume | 2018-October |
| ISSN (Print) | 2159-3442 |
| ISSN (Electronic) | 2159-3450 |
Conference
| Conference | 2018 IEEE Region 10 Conference, TENCON 2018 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 18/10/28 → 18/10/31 |
Fingerprint
Keywords
- approximate multiplier
- Compressor
- high performance
- Input reordering
- low power
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering
Cite this
Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering. / Liu, Zhenhao; Guo, Yi; Sun, Xiaoting; Kimura, Shinji.
Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 545-550 8650340 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2018-October).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering
AU - Liu, Zhenhao
AU - Guo, Yi
AU - Sun, Xiaoting
AU - Kimura, Shinji
PY - 2019/2/22
Y1 - 2019/2/22
N2 - Today in nanometer regime, approximate circuits have attracted much more attention due to the pursuit of low power consumption and high performance. Approximate multiplier is the key arithmetic function in many error-tolerant applications such as signal processing. In this paper, two approximate compressors based on input reordering logic have been proposed for the partial product reduction in the multiplication. A 2-bit reordering circuit is also designed for the proposed multiplier. Experimental results show that the proposed multiplier sacrifices only a small amount of precision (about 0.58%) to drastically reduce power, area, and delay up to (36.6%), (28.8%) and (20.1%) compared to accurate Wallace multiplier. The proposed multiplier achieves a high signal-to-noise ratio (over 50dB) when applied to an image processing algorithm.
AB - Today in nanometer regime, approximate circuits have attracted much more attention due to the pursuit of low power consumption and high performance. Approximate multiplier is the key arithmetic function in many error-tolerant applications such as signal processing. In this paper, two approximate compressors based on input reordering logic have been proposed for the partial product reduction in the multiplication. A 2-bit reordering circuit is also designed for the proposed multiplier. Experimental results show that the proposed multiplier sacrifices only a small amount of precision (about 0.58%) to drastically reduce power, area, and delay up to (36.6%), (28.8%) and (20.1%) compared to accurate Wallace multiplier. The proposed multiplier achieves a high signal-to-noise ratio (over 50dB) when applied to an image processing algorithm.
KW - approximate multiplier
KW - Compressor
KW - high performance
KW - Input reordering
KW - low power
UR - http://www.scopus.com/inward/record.url?scp=85063188717&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063188717&partnerID=8YFLogxK
U2 - 10.1109/TENCON.2018.8650340
DO - 10.1109/TENCON.2018.8650340
M3 - Conference contribution
AN - SCOPUS:85063188717
T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON
SP - 545
EP - 550
BT - Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -