Approximate computing has emerged as a promising approach to reduce energy by sacrificing some accuracy in error-tolerant applications. For these applications, multiplication is a key fundamental operation. In the paper, we propose an approximate signed multiplier design with a low power consumption and a short critical path. Inexact sign-focused compressors are first proposed to accumulate partial products, which cut the carry propagation and simplify the circuit complexity. Moreover, three types of approximate multipliers are presented to achieve different trade-offs between accuracy loss and hardware saving. Experimental results show that the most accurate proposed multiplier reduces power by 52.44%, area by 37.73%, and delay by 22.14%, compare with the exact signed multiplier. In addition, the proposed multiplier design costs less hardware than other multipliers with a comparable accuracy. At last, an application to image processing shows the efficiency of proposed signed multipliers.