Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

Hiroyuki Akasaka, Shin Ya Abe, Masao Yanagisawa, Nozomu Togawa

    Research output: Contribution to journalArticle

    Abstract

    With the miniaturization and high performance of current and future LSIs, demand for portable devices has much more increased. Especially the problems of battery runtime and device overheating have occurred. In addition, with the downsize of the LSI design process, the ratio of an interconnection delay to a gate delay has continued to increase. High-level synthesis to estimate the interconnection delays and reduce energy consumption is essential. In this paper, we propose a high-level synthesis algorithm based on HDR architectures (huddle-based distributed register architectures) utilizing multi-stage clock gating. By increasing the number of clock gating stages in each huddle, we increase the number of the control steps at which we can apply the clock gating to registers. We can determine the configuration of the clock gating with optimized energy consumption. The experimental results demonstrate that our proposed algorithm reduced energy consumption by up to 27.7% compared with conventional algorithms.

    Original languageEnglish
    Pages (from-to)74-80
    Number of pages7
    JournalIPSJ Transactions on System LSI Design Methodology
    Volume7
    DOIs
    Publication statusPublished - 2014

    Keywords

    • Clock gating timing
    • Gating step count
    • High-level synthesis
    • Huddle-based distributed register architecture
    • Multi-stage clock gating

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications

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