Energy-efficient high-level synthesis for HDR architectures with clock gating

Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, the problems for battery runtime and device overheating have occurred. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate the interconnection delay and reduce energy consumption even in a high-level synthesis stage. Recently, an HDR architecture and its associated power-optimized high-level synthesis algorithm have been proposed which can effectively estimate the interconnection delays by introducing the idea of 'huddles' into an LSI chip. It utilize multiple supply voltages and achieves power-optimized LSI synthesis but does not take into account the clock gatings. In this paper, we propose a high-level synthesis algorithm based on HDR architectures utilizing clock gatings. Firstly we focus on the number of the control steps at which we can apply the clock gating to registers. Secondly, we synthesize the huddles such that each of the synthesized huddles includes registers which have similar or exactly the same clock gating timings. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 14.9% compared with the conventional algorithm.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages135-138
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Conference

Conference2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Akasaka, H., Yanagisawa, M., & Togawa, N. (2012). Energy-efficient high-level synthesis for HDR architectures with clock gating. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 135-138). [6407058] (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407058