Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

Original languageEnglish
Title of host publication2013 IEEE 10th International Conference on ASIC, ASICON 2013
PublisherIEEE Computer Society
ISBN (Print)9781467364157
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China
Duration: 2013 Oct 282013 Oct 31

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CountryChina
CityShenzhen
Period13/10/2813/10/31

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N., & Sugibayashi, T. (2013). Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. In 2013 IEEE 10th International Conference on ASIC, ASICON 2013 [6811826] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811826