Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno; Masashi Tawada; Masao Yanagisawa; Shinji Kimura; Nozomu Togawa; Tadahiko Sugibayashi

doi:10.1109/ASICON.2013.6811826

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

Original language	English
Title of host publication	2013 IEEE 10th International Conference on ASIC, ASICON 2013
Publisher	IEEE Computer Society
ISBN (Print)	9781467364157
DOIs	https://doi.org/10.1109/ASICON.2013.6811826
Publication status	Published - 2013 Jan 1
Event	2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China Duration: 2013 Oct 28 → 2013 Oct 31

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Other

Other	2013 IEEE 10th International Conference on ASIC, ASICON 2013
Country/Territory	China
City	Shenzhen
Period	13/10/28 → 13/10/31

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ASICON.2013.6811826

Cite this

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N., & Sugibayashi, T. (2013). Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. In 2013 IEEE 10th International Conference on ASIC, ASICON 2013 [6811826] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811826

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. / Matsuno, Shota; Tawada, Masashi ; Yanagisawa, Masao et al.

2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 2013. 6811826 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsuno, S, Tawada, M , Yanagisawa, M , Kimura, S , Togawa, N & Sugibayashi, T 2013, Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. in 2013 IEEE 10th International Conference on ASIC, ASICON 2013., 6811826, Proceedings of International Conference on ASIC, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811826

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AB - As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.

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Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Abstract

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ASJC Scopus subject areas

UN SDGs

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