Enhancement of drain current in planar MOSFETs by dopant profile engineering using nonmelt laser spike annealing

Akio Shima, Toshiyuki Mine, Kazuyoshi Torii, Atsushi Hiraiwa

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/ drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.

Original languageEnglish
Pages (from-to)2953-2959
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume54
Issue number11
DOIs
Publication statusPublished - 2007 Nov
Externally publishedYes

Fingerprint

Drain current
spikes
field effect transistors
Doping (additives)
engineering
Annealing
annealing
implantation
Lasers
augmentation
profiles
Rapid thermal annealing
lasers
halos
Germanium
Reengineering
Hot carriers
Chemical activation
diffusion length
Fabrication

Keywords

  • CMOS integrated circuits
  • Junctions
  • Laser annealing
  • Source/drain (S/D) extensions (SDEs)
  • Strained silicon
  • Very-large-scale integration (VLSI)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Enhancement of drain current in planar MOSFETs by dopant profile engineering using nonmelt laser spike annealing. / Shima, Akio; Mine, Toshiyuki; Torii, Kazuyoshi; Hiraiwa, Atsushi.

In: IEEE Transactions on Electron Devices, Vol. 54, No. 11, 11.2007, p. 2953-2959.

Research output: Contribution to journalArticle

Shima, Akio ; Mine, Toshiyuki ; Torii, Kazuyoshi ; Hiraiwa, Atsushi. / Enhancement of drain current in planar MOSFETs by dopant profile engineering using nonmelt laser spike annealing. In: IEEE Transactions on Electron Devices. 2007 ; Vol. 54, No. 11. pp. 2953-2959.
@article{4235da09955e402f8938a54e79843d48,
title = "Enhancement of drain current in planar MOSFETs by dopant profile engineering using nonmelt laser spike annealing",
abstract = "We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10{\%} and 20{\%} better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/ drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.",
keywords = "CMOS integrated circuits, Junctions, Laser annealing, Source/drain (S/D) extensions (SDEs), Strained silicon, Very-large-scale integration (VLSI)",
author = "Akio Shima and Toshiyuki Mine and Kazuyoshi Torii and Atsushi Hiraiwa",
year = "2007",
month = "11",
doi = "10.1109/TED.2007.906972",
language = "English",
volume = "54",
pages = "2953--2959",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - Enhancement of drain current in planar MOSFETs by dopant profile engineering using nonmelt laser spike annealing

AU - Shima, Akio

AU - Mine, Toshiyuki

AU - Torii, Kazuyoshi

AU - Hiraiwa, Atsushi

PY - 2007/11

Y1 - 2007/11

N2 - We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/ drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.

AB - We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/ drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.

KW - CMOS integrated circuits

KW - Junctions

KW - Laser annealing

KW - Source/drain (S/D) extensions (SDEs)

KW - Strained silicon

KW - Very-large-scale integration (VLSI)

UR - http://www.scopus.com/inward/record.url?scp=36249023175&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=36249023175&partnerID=8YFLogxK

U2 - 10.1109/TED.2007.906972

DO - 10.1109/TED.2007.906972

M3 - Article

AN - SCOPUS:36249023175

VL - 54

SP - 2953

EP - 2959

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 11

ER -