Error rate decrease through hamming weight change for NAND flash

Chong Zhang, Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.

    Original languageEnglish
    Title of host publicationISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
    Pages1079-1082
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010 - Tokyo
    Duration: 2010 Oct 262010 Oct 29

    Other

    Other2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
    CityTokyo
    Period10/10/2610/10/29

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Information Systems

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  • Cite this

    Zhang, C., Huang, M., Okamura, L., & Yoshihara, T. (2010). Error rate decrease through hamming weight change for NAND flash. In ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies (pp. 1079-1082). [5665147] https://doi.org/10.1109/ISCIT.2010.5665147