Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.

    Original languageEnglish
    Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Pages247-250
    Number of pages4
    DOIs
    Publication statusPublished - 2011
    Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu
    Duration: 2011 Apr 252011 Apr 28

    Other

    Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    CityHsinchu
    Period11/4/2511/4/28

    Fingerprint

    Embedded systems
    Simulators
    Hardware
    Costs
    Experiments

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Tawada, M., Yanagisawa, M., Ohtsuki, T., & Togawa, N. (2011). Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 247-250). [5783622] https://doi.org/10.1109/VDAT.2011.5783622

    Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. / Tawada, Masashi; Yanagisawa, Masao; Ohtsuki, Tatsuo; Togawa, Nozomu.

    Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 247-250 5783622.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tawada, M, Yanagisawa, M, Ohtsuki, T & Togawa, N 2011, Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783622, pp. 247-250, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, 11/4/25. https://doi.org/10.1109/VDAT.2011.5783622
    Tawada M, Yanagisawa M, Ohtsuki T, Togawa N. Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 247-250. 5783622 https://doi.org/10.1109/VDAT.2011.5783622
    Tawada, Masashi ; Yanagisawa, Masao ; Ohtsuki, Tatsuo ; Togawa, Nozomu. / Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. pp. 247-250
    @inproceedings{4c1c140bfc8a42ae8fc57cc23b1f7f51,
    title = "Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies",
    abstract = "Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.",
    author = "Masashi Tawada and Masao Yanagisawa and Tatsuo Ohtsuki and Nozomu Togawa",
    year = "2011",
    doi = "10.1109/VDAT.2011.5783622",
    language = "English",
    isbn = "9781424484997",
    pages = "247--250",
    booktitle = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

    }

    TY - GEN

    T1 - Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

    AU - Tawada, Masashi

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    AU - Togawa, Nozomu

    PY - 2011

    Y1 - 2011

    N2 - Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.

    AB - Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.

    UR - http://www.scopus.com/inward/record.url?scp=79959533889&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=79959533889&partnerID=8YFLogxK

    U2 - 10.1109/VDAT.2011.5783622

    DO - 10.1109/VDAT.2011.5783622

    M3 - Conference contribution

    AN - SCOPUS:79959533889

    SN - 9781424484997

    SP - 247

    EP - 250

    BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    ER -