Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Masashi Tawada; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa

doi:10.1109/VDAT.2011.5783622

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Masashi Tawada^*, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	247-250
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783622
Publication status	Published - 2011 Jun 28
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan, Province of China Duration: 2011 Apr 25 → 2011 Apr 28

Publication series

Name	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	11/4/25 → 11/4/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VDAT.2011.5783622

Cite this

Tawada, M., Yanagisawa, M., Ohtsuki, T., & Togawa, N. (2011). Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 247-250). [5783622] (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783622

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. / Tawada, Masashi ; Yanagisawa, Masao; Ohtsuki, Tatsuo et al.

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 247-250 5783622 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tawada, M , Yanagisawa, M, Ohtsuki, T & Togawa, N 2011, Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783622, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, pp. 247-250, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, Province of China, 11/4/25. https://doi.org/10.1109/VDAT.2011.5783622

Tawada M , Yanagisawa M, Ohtsuki T, Togawa N. Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 247-250. 5783622. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). doi: 10.1109/VDAT.2011.5783622

Tawada, Masashi ; Yanagisawa, Masao ; Ohtsuki, Tatsuo et al. / Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies. Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. pp. 247-250 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

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Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

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