Exact and fast L1 cache simulation for embedded systems

Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    25 Citations (Scopus)

    Abstract

    In recent years, the gap between the cycle time of processors and memory access time has been increasing. One of the solutions to solve this problem is to use a cache. But just using a large cache may not reduce the total memory access time. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: a cache set size, a line size, and an associativity. In this paper, we propose two exact cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but increase simulation speed dramatically. By using our approach, the number of cache hit/miss judgments required for simulating all the cache configurations is reduced to 31.4%-93.6% compared to conventional approaches. As a result, our proposed approach totally runs an average of 1.8 times faster and a maximum of 3.3 times faster compared to the fastest approach proposed so far. Our proposed exact cache simulation approach achieves the world fastest L1 cache simulation.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages817-822
    Number of pages6
    DOIs
    Publication statusPublished - 2009
    EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama
    Duration: 2009 Jan 192009 Jan 22

    Other

    OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
    CityYokohama
    Period09/1/1909/1/22

    Fingerprint

    Embedded systems
    Data storage equipment

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    Cite this

    Tojo, N., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2009). Exact and fast L1 cache simulation for embedded systems. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 817-822). [4796581] https://doi.org/10.1109/ASPDAC.2009.4796581

    Exact and fast L1 cache simulation for embedded systems. / Tojo, Nobuaki; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 817-822 4796581.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tojo, N, Togawa, N, Yanagisawa, M & Ohtsuki, T 2009, Exact and fast L1 cache simulation for embedded systems. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4796581, pp. 817-822, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796581
    Tojo N, Togawa N, Yanagisawa M, Ohtsuki T. Exact and fast L1 cache simulation for embedded systems. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 817-822. 4796581 https://doi.org/10.1109/ASPDAC.2009.4796581
    Tojo, Nobuaki ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Exact and fast L1 cache simulation for embedded systems. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. pp. 817-822
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