Exact minimization of free bdds and its application to pass-transistor logic optimization

Kazuyoshi Takagi, Hiroshi Hatakeda, Shinji Kimura, Katsumasa Watanabe

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In several design methods for Pass-transistor Logic (PTL) circuits Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

Original languageEnglish
Pages (from-to)2407-2413
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE82-A
Issue number11
Publication statusPublished - 1999
Externally publishedYes

Fingerprint

Transistors
Logic
Logic Synthesis
Boolean functions
Optimization
Boolean Functions
Equivalence classes
Logic circuits
Equivalence class
Design Method
Statistics
Synthesis
Benchmark
Path
Networks (circuits)
Cell
Vertex of a graph

Keywords

  • Boolean function
  • Free bdd
  • Logic minimization
  • Pass-transistor logic

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Exact minimization of free bdds and its application to pass-transistor logic optimization. / Takagi, Kazuyoshi; Hatakeda, Hiroshi; Kimura, Shinji; Watanabe, Katsumasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E82-A, No. 11, 1999, p. 2407-2413.

Research output: Contribution to journalArticle

@article{41c2391df44d483da513b9931178537e,
title = "Exact minimization of free bdds and its application to pass-transistor logic optimization",
abstract = "In several design methods for Pass-transistor Logic (PTL) circuits Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56{\%} of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5{\%} size reduction.",
keywords = "Boolean function, Free bdd, Logic minimization, Pass-transistor logic",
author = "Kazuyoshi Takagi and Hiroshi Hatakeda and Shinji Kimura and Katsumasa Watanabe",
year = "1999",
language = "English",
volume = "E82-A",
pages = "2407--2413",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - Exact minimization of free bdds and its application to pass-transistor logic optimization

AU - Takagi, Kazuyoshi

AU - Hatakeda, Hiroshi

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 1999

Y1 - 1999

N2 - In several design methods for Pass-transistor Logic (PTL) circuits Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

AB - In several design methods for Pass-transistor Logic (PTL) circuits Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

KW - Boolean function

KW - Free bdd

KW - Logic minimization

KW - Pass-transistor logic

UR - http://www.scopus.com/inward/record.url?scp=0011839259&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0011839259&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0011839259

VL - E82-A

SP - 2407

EP - 2413

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 11

ER -