Experimental 1 Mb cache DRAM with ECC

Mikio Asakura; Yoshio Matsuda; Hideto Hidaka; Yoshinori Tanaka; Kazuyasu Fujishima; Tsutomu Yoshihara

Experimental 1 Mb cache DRAM with ECC

Mikio Asakura^*, Yoshio Matsuda, Hideto Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.

Original language	English
Title of host publication	Symp VLSI Circuit 1989
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	43-44
Number of pages	2
Publication status	Published - 1989
Externally published	Yes
Event	Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 1989 May 25 → 1989 May 27

Other

Other	Symposium on VLSI Circuits 1989
City	Kyoto, Japan
Period	89/5/25 → 89/5/27

ASJC Scopus subject areas

Engineering(all)

Cite this

@inproceedings{d6682563c03a4e22bb90ec4391373d70,

title = "Experimental 1 Mb cache DRAM with ECC",

abstract = "The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.",

author = "Mikio Asakura and Yoshio Matsuda and Hideto Hidaka and Yoshinori Tanaka and Kazuyasu Fujishima and Tsutomu Yoshihara",

year = "1989",

language = "English",

pages = "43--44",

editor = "Anon",

booktitle = "Symp VLSI Circuit 1989",

publisher = "Publ by IEEE",

note = "Symposium on VLSI Circuits 1989 ; Conference date: 25-05-1989 Through 27-05-1989",

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TY - GEN

T1 - Experimental 1 Mb cache DRAM with ECC

AU - Asakura, Mikio

AU - Matsuda, Yoshio

AU - Hidaka, Hideto

AU - Tanaka, Yoshinori

AU - Fujishima, Kazuyasu

AU - Yoshihara, Tsutomu

PY - 1989

Y1 - 1989

N2 - The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.

AB - The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.

UR - http://www.scopus.com/inward/record.url?scp=0024925779&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024925779&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024925779

SP - 43

EP - 44

BT - Symp VLSI Circuit 1989

A2 - Anon, null

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - Symposium on VLSI Circuits 1989

Y2 - 25 May 1989 through 27 May 1989

ER -

Experimental 1 Mb cache DRAM with ECC

Abstract

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ASJC Scopus subject areas

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