Experimental 1 Mb cache DRAM with ECC

Mikio Asakura, Yoshio Matsuda, Hideto Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.

Original languageEnglish
Title of host publicationSymp VLSI Circuit 1989
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages43-44
Number of pages2
Publication statusPublished - 1989
Externally publishedYes
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 1989 May 251989 May 27

Other

OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period89/5/2589/5/27

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Asakura, M., Matsuda, Y., Hidaka, H., Tanaka, Y., Fujishima, K., & Yoshihara, T. (1989). Experimental 1 Mb cache DRAM with ECC. In Anon (Ed.), Symp VLSI Circuit 1989 (pp. 43-44). Publ by IEEE.