Abstract
The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.
Original language | English |
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Title of host publication | Symp VLSI Circuit 1989 |
Editors | Anon |
Place of Publication | Piscataway, NJ, United States |
Publisher | Publ by IEEE |
Pages | 43-44 |
Number of pages | 2 |
Publication status | Published - 1989 |
Externally published | Yes |
Event | Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 1989 May 25 → 1989 May 27 |
Other
Other | Symposium on VLSI Circuits 1989 |
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City | Kyoto, Japan |
Period | 89/5/25 → 89/5/27 |
ASJC Scopus subject areas
- Engineering(all)