Abstract
The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.
| Original language | English |
|---|---|
| Title of host publication | Symp VLSI Circuit 1989 |
| Editors | Anon |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | Publ by IEEE |
| Pages | 43-44 |
| Number of pages | 2 |
| Publication status | Published - 1989 |
| Externally published | Yes |
| Event | Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 1989 May 25 → 1989 May 27 |
Other
| Other | Symposium on VLSI Circuits 1989 |
|---|---|
| City | Kyoto, Japan |
| Period | 89/5/25 → 89/5/27 |
Fingerprint
ASJC Scopus subject areas
- Engineering(all)
Cite this
Experimental 1 Mb cache DRAM with ECC. / Asakura, Mikio; Matsuda, Yoshio; Hidaka, Hideto; Tanaka, Yoshinori; Fujishima, Kazuyasu; Yoshihara, Tsutomu.
Symp VLSI Circuit 1989. ed. / Anon. Piscataway, NJ, United States : Publ by IEEE, 1989. p. 43-44.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Experimental 1 Mb cache DRAM with ECC
AU - Asakura, Mikio
AU - Matsuda, Yoshio
AU - Hidaka, Hideto
AU - Tanaka, Yoshinori
AU - Fujishima, Kazuyasu
AU - Yoshihara, Tsutomu
PY - 1989
Y1 - 1989
N2 - The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.
AB - The authors describe a cache DRAM (dynamic RAM) with an ECC (error checking and correcting) circuit. This ECC circuit improves the reliability of the DRAM data. An on-chip cache scheme can provide a high-speed data mapping and relieve access time loss for error correction, thus reducing the average access time. It is shown that a 4-MB main memory system with 32-kB cache memory and 32-b parallel I/Os can be constructed with thirty-two 1-Mb cache DRAM chips or eight 4-Mb cache DRAM chips using the proposed scheme.
UR - http://www.scopus.com/inward/record.url?scp=0024925779&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0024925779&partnerID=8YFLogxK
M3 - Conference contribution
SP - 43
EP - 44
BT - Symp VLSI Circuit 1989
A2 - Anon, null
PB - Publ by IEEE
CY - Piscataway, NJ, United States
ER -