Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori

Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama^*, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

Original language	English
Pages (from-to)	4.4/1-4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1988
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.",

abstract = "A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.",

author = "Tohru Furuyama and Takashi Ohsawa and Yousei Nagahama and Hiroto Tanaka and Yohji Watanabe and Tohru Kimura and Kazuyoshi Muraoka and Kenji Natori",

year = "1988",

language = "English",

pages = "4.4/1--4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

AU - Furuyama, Tohru

AU - Ohsawa, Takashi

AU - Nagahama, Yousei

AU - Tanaka, Hiroto

AU - Watanabe, Yohji

AU - Kimura, Tohru

AU - Muraoka, Kazuyoshi

AU - Natori, Kenji

PY - 1988

Y1 - 1988

N2 - A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

AB - A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

UR - http://www.scopus.com/inward/record.url?scp=0024143504&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024143504&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024143504

SN - 0886-5930

SP - 4.4/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

ER -

Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Abstract

ASJC Scopus subject areas

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