Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

Original languageEnglish
Pages (from-to)4.4/1-4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1988 Dec 1

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Furuyama, T., Ohsawa, T., Nagahama, Y., Tanaka, H., Watanabe, Y., Kimura, T., Muraoka, K., & Natori, K. (1988). Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application. Proceedings of the Custom Integrated Circuits Conference, 4.4/1-4.