Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

Original languageEnglish
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1988
Externally publishedYes

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Dynamic random access storage
Macros
Data storage equipment
Random access storage
Defects

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application. / Furuyama, Tohru; Ohsawa, Takashi; Nagahama, Yousei; Tanaka, Hiroto; Watanabe, Yohji; Kimura, Tohru; Muraoka, Kazuyoshi; Natori, Kenji.

In: Proceedings of the Custom Integrated Circuits Conference, 1988.

Research output: Contribution to journalArticle

Furuyama, Tohru ; Ohsawa, Takashi ; Nagahama, Yousei ; Tanaka, Hiroto ; Watanabe, Yohji ; Kimura, Tohru ; Muraoka, Kazuyoshi ; Natori, Kenji. / Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application. In: Proceedings of the Custom Integrated Circuits Conference. 1988.
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