Experimental 256-Mb DRAM with boosted sense-ground scheme

Mikio Asakura*, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)

Abstract

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.

Original languageEnglish
Pages (from-to)1303-1309
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number11
DOIs
Publication statusPublished - 1994 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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