In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.
ASJC Scopus subject areas
- Electrical and Electronic Engineering