Experimental 256-Mb DRAM with boosted sense-ground scheme

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm2 and a performance of 34 ns access time.

Original languageEnglish
Pages (from-to)1303-1309
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number11
DOIs
Publication statusPublished - 1994 Nov
Externally publishedYes

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Dynamic random access storage
Semiconductor devices
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Asakura, M., Ooishi, T., Tsukude, M., Tomishima, S., Eimori, T., Hidaka, H., ... Yoshihara, T. (1994). Experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE Journal of Solid-State Circuits, 29(11), 1303-1309. https://doi.org/10.1109/4.328628

Experimental 256-Mb DRAM with boosted sense-ground scheme. / Asakura, Mikio; Ooishi, Tsukasa; Tsukude, Masaki; Tomishima, Shigeki; Eimori, Takahisa; Hidaka, Hideto; Ohno, Yoshikazu; Arimoto, Kazutani; Fujishima, Kazuyasu; Nishimura, Tadashi; Yoshihara, Tsutomu.

In: IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, 11.1994, p. 1303-1309.

Research output: Contribution to journalArticle

Asakura, M, Ooishi, T, Tsukude, M, Tomishima, S, Eimori, T, Hidaka, H, Ohno, Y, Arimoto, K, Fujishima, K, Nishimura, T & Yoshihara, T 1994, 'Experimental 256-Mb DRAM with boosted sense-ground scheme', IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1303-1309. https://doi.org/10.1109/4.328628
Asakura M, Ooishi T, Tsukude M, Tomishima S, Eimori T, Hidaka H et al. Experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE Journal of Solid-State Circuits. 1994 Nov;29(11):1303-1309. https://doi.org/10.1109/4.328628
Asakura, Mikio ; Ooishi, Tsukasa ; Tsukude, Masaki ; Tomishima, Shigeki ; Eimori, Takahisa ; Hidaka, Hideto ; Ohno, Yoshikazu ; Arimoto, Kazutani ; Fujishima, Kazuyasu ; Nishimura, Tadashi ; Yoshihara, Tsutomu. / Experimental 256-Mb DRAM with boosted sense-ground scheme. In: IEEE Journal of Solid-State Circuits. 1994 ; Vol. 29, No. 11. pp. 1303-1309.
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