Experimental evaluation of high-level energy optimization based on thread partitioning

Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper presents a thread partitioning algorithm for high-level synthesis systems which generate low energy circuits. In the algorithm, we partitions a thread into two sub-threads, one of which has RF and the other does not have RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. We achieve 33% energy reduction when we apply our proposed algorithm to a JPEG encoder.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    Pages161-164
    Number of pages4
    Volume1
    Publication statusPublished - 2004
    Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan
    Duration: 2004 Dec 62004 Dec 9

    Other

    Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    CityTainan
    Period04/12/604/12/9

    Fingerprint

    Electron energy levels
    Clocks
    Synchronization
    Networks (circuits)
    High level synthesis

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2004). Experimental evaluation of high-level energy optimization based on thread partitioning. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (Vol. 1, pp. 161-164)

    Experimental evaluation of high-level energy optimization based on thread partitioning. / Uchida, Jumpei; Miyaoka, Yuichiro; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1 2004. p. 161-164.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Uchida, J, Miyaoka, Y, Togawa, N, Yanagisawa, M & Ohtsuki, T 2004, Experimental evaluation of high-level energy optimization based on thread partitioning. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. vol. 1, pp. 161-164, 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, 04/12/6.
    Uchida J, Miyaoka Y, Togawa N, Yanagisawa M, Ohtsuki T. Experimental evaluation of high-level energy optimization based on thread partitioning. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. 2004. p. 161-164
    Uchida, Jumpei ; Miyaoka, Yuichiro ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Experimental evaluation of high-level energy optimization based on thread partitioning. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1 2004. pp. 161-164
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