Abstract
Programming the multiprocessor system-on-chip (MP-SoC) requires partitioning the sequential reference programs onto multiple processors running in parallel. However, designers still need to partition the code manually due to the lack of automated partition techniques. To settle this issue, this paper proposes a partition exploration algorithm based on the search space smoothing techniques, and implements the proposed method using a commercial extensible processor (Xtensa LX2 processor from Tensilica Inc.). We have Verified the feasibility of the algorithm by implementing the MPEG2 benchmark on the Xtensa-based two-processor system. The final experimental results indicate a performance improvement of at least 1.6× compared to the single-processor system.
Original language | English |
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Pages (from-to) | 2456-2464 |
Number of pages | 9 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E91-A |
Issue number | 9 |
DOIs | |
Publication status | Published - 2008 Sept |
Keywords
- ASIP
- CAD algorithm
- Hardware/software partitioning
- MPSoC
- Search space smoothing
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing