Fabrication of three dimensional silicon slopes using mask With square openings

Yusuke Takei, Takahiro Ohori, Tomoyuki Takahata, Tetsuo Kan, Eiji Iwase, Kiyoshi Matsumoto, Isao Shimoyama

Research output: Contribution to journalArticle

Abstract

We propose a fabrication method of three-dimensional silicon slopes using RIE-lag. RIE-lag is a lag of an etching rate depending on square openings area of a mask. We measured relationship between area of square openings and etched depths. We confirmed that etched depths were defined as a function of the square openings. With this relationship, we designed a mask with various sizes of the squares for slope structures. Square openings of various sizes were patterned using EB lithography. Silicon was etched vertically with ICP-RIE (Inductive Coupled Plasma - Reactive Ion Etching). By RIE-lag, trenches with multiple depths depending on the area of the square openings were formed. Silicon surface was smoothed by SF6 isotropic dry etching. As a result, by the combination of ICP-RIE anisotropic etching RIE-lag and SF6 isotropic etching, we fabricated 57° silicon slopes of surface roughness 10 nm in plane and 35 nm in slope surface.

Original languageEnglish
JournalIEEJ Transactions on Sensors and Micromachines
Volume130
Issue number5
DOIs
Publication statusPublished - 2010
Externally publishedYes

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Keywords

  • ICP-RIE
  • RIE-lag
  • Square openings
  • Three dimensional structures

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanical Engineering

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