Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara, Takashi Matsukawa, Kenichi Ishii, Yongxun Liu, Masayoshi Nagao, Hisao Tanoue, Takashi Tanii, Iwao Ohdomari, Seigo Kanemaru, Eiichi Suzuki

Research output: Contribution to journalArticle

11 Citations (Scopus)


It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

Original languageEnglish
Pages (from-to)1916-1918
Number of pages3
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number4 B
Publication statusPublished - 2003 Apr 1



  • Ion implantation
  • Ion-bombardment-retarded etching of Si
  • TMAH
  • Ultrathin Si wall
  • Vertical double-gate MOSFET
  • Wet etching

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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