Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Meishoku Masahara, Takashi Matsukawa, Kenichi Ishii, Yongxun Liu, Masayoshi Nagao, Hisao Tanoue, Takashi Tanii, Iwao Ohdomari, Seigo Kanemaru, Eiichi Suzuki

    Research output: Contribution to journalArticle

    11 Citations (Scopus)

    Abstract

    It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

    Original languageEnglish
    Pages (from-to)1916-1918
    Number of pages3
    JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
    Volume42
    Issue number4 B
    Publication statusPublished - 2003 Apr

    Fingerprint

    MOSFET devices
    Ion bombardment
    metal oxide semiconductors
    bombardment
    Etching
    field effect transistors
    etching
    Fabrication
    fabrication
    Dry etching
    Ion implantation
    damage
    ions
    hydroxides
    ion implantation
    Substrates
    simulation

    Keywords

    • Ion implantation
    • Ion-bombardment-retarded etching of Si
    • TMAH
    • Ultrathin Si wall
    • Vertical double-gate MOSFET
    • Wet etching

    ASJC Scopus subject areas

    • Physics and Astronomy (miscellaneous)

    Cite this

    Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). / Masahara, Meishoku; Matsukawa, Takashi; Ishii, Kenichi; Liu, Yongxun; Nagao, Masayoshi; Tanoue, Hisao; Tanii, Takashi; Ohdomari, Iwao; Kanemaru, Seigo; Suzuki, Eiichi.

    In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 42, No. 4 B, 04.2003, p. 1916-1918.

    Research output: Contribution to journalArticle

    Masahara, Meishoku ; Matsukawa, Takashi ; Ishii, Kenichi ; Liu, Yongxun ; Nagao, Masayoshi ; Tanoue, Hisao ; Tanii, Takashi ; Ohdomari, Iwao ; Kanemaru, Seigo ; Suzuki, Eiichi. / Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE). In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2003 ; Vol. 42, No. 4 B. pp. 1916-1918.
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    abstract = "It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.",
    keywords = "Ion implantation, Ion-bombardment-retarded etching of Si, TMAH, Ultrathin Si wall, Vertical double-gate MOSFET, Wet etching",
    author = "Meishoku Masahara and Takashi Matsukawa and Kenichi Ishii and Yongxun Liu and Masayoshi Nagao and Hisao Tanoue and Takashi Tanii and Iwao Ohdomari and Seigo Kanemaru and Eiichi Suzuki",
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    AU - Masahara, Meishoku

    AU - Matsukawa, Takashi

    AU - Ishii, Kenichi

    AU - Liu, Yongxun

    AU - Nagao, Masayoshi

    AU - Tanoue, Hisao

    AU - Tanii, Takashi

    AU - Ohdomari, Iwao

    AU - Kanemaru, Seigo

    AU - Suzuki, Eiichi

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    AB - It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

    KW - Ion implantation

    KW - Ion-bombardment-retarded etching of Si

    KW - TMAH

    KW - Ultrathin Si wall

    KW - Vertical double-gate MOSFET

    KW - Wet etching

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