FAST 8K multiplied by 8 MIXED CMOS STATIC RAM.

Hirofumi Shinohara, Kenji Anami, Tsutomu Yoshihara, Yuji Kihara, Yoshio Kohno, Yoichi Akasaka, Shinpei Kayano

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2- mu m design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266. 5 mu m**2 and design of the die in 34. 3 mm**2 .

Original languageEnglish
Pages (from-to)1792-1796
Number of pages5
JournalIEEE Transactions on Electron Devices
VolumeED-32
Issue number9
Publication statusPublished - 1985 Sep
Externally publishedYes

Fingerprint

access time
Random access storage
CMOS
Data storage equipment
cells
immunity
Polysilicon
layouts
amplifiers
chips
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Shinohara, H., Anami, K., Yoshihara, T., Kihara, Y., Kohno, Y., Akasaka, Y., & Kayano, S. (1985). FAST 8K multiplied by 8 MIXED CMOS STATIC RAM. IEEE Transactions on Electron Devices, ED-32(9), 1792-1796.

FAST 8K multiplied by 8 MIXED CMOS STATIC RAM. / Shinohara, Hirofumi; Anami, Kenji; Yoshihara, Tsutomu; Kihara, Yuji; Kohno, Yoshio; Akasaka, Yoichi; Kayano, Shinpei.

In: IEEE Transactions on Electron Devices, Vol. ED-32, No. 9, 09.1985, p. 1792-1796.

Research output: Contribution to journalArticle

Shinohara, H, Anami, K, Yoshihara, T, Kihara, Y, Kohno, Y, Akasaka, Y & Kayano, S 1985, 'FAST 8K multiplied by 8 MIXED CMOS STATIC RAM.', IEEE Transactions on Electron Devices, vol. ED-32, no. 9, pp. 1792-1796.
Shinohara H, Anami K, Yoshihara T, Kihara Y, Kohno Y, Akasaka Y et al. FAST 8K multiplied by 8 MIXED CMOS STATIC RAM. IEEE Transactions on Electron Devices. 1985 Sep;ED-32(9):1792-1796.
Shinohara, Hirofumi ; Anami, Kenji ; Yoshihara, Tsutomu ; Kihara, Yuji ; Kohno, Yoshio ; Akasaka, Yoichi ; Kayano, Shinpei. / FAST 8K multiplied by 8 MIXED CMOS STATIC RAM. In: IEEE Transactions on Electron Devices. 1985 ; Vol. ED-32, No. 9. pp. 1792-1796.
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