TY - JOUR
T1 - Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC
AU - Sun, Heming
AU - Zhou, Dajiang
AU - Hu, Landan
AU - Kimura, Shinji
AU - Goto, Satoshi
N1 - Funding Information:
Manuscript received September 22, 2016; revised January 21, 2017 and March 15, 2017; accepted April 18, 2017. Date of publication May 3, 2017; date of current version October 13, 2017. This work was supported by the Graduate Program for Embodiment Informatics of the Ministry of Education, Culture, Sports, Science and Technology. The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Jun Wu. (Corresponding author: Dajiang Zhou.) H. Sun, D. Zhou, S. Kimura, and S. Goto are with the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu 808-0135, Japan (e-mail: terrysun1989@akane.waseda.jp; zhou@fuji.waseda.jp; shinji_kimura@waseda.jp; goto@waseda.jp).
Publisher Copyright:
© 1999-2012 IEEE.
PY - 2017/11
Y1 - 2017/11
N2 - In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra-and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the 'all-intra' configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.
AB - In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra-and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the 'all-intra' configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.
KW - Encoding
KW - high efficiency video coding (HEVC)
KW - rate distortion optimization (RDO)
KW - video coding
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U2 - 10.1109/TMM.2017.2700629
DO - 10.1109/TMM.2017.2700629
M3 - Article
AN - SCOPUS:85032209621
VL - 19
SP - 2375
EP - 2390
JO - IEEE Transactions on Multimedia
JF - IEEE Transactions on Multimedia
SN - 1520-9210
IS - 11
M1 - 7918540
ER -