Abstract
In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra-and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the 'all-intra' configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.
| Original language | English |
|---|---|
| Article number | 7918540 |
| Pages (from-to) | 2375-2390 |
| Number of pages | 16 |
| Journal | IEEE Transactions on Multimedia |
| Volume | 19 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - 2017 Nov 1 |
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Keywords
- Encoding
- high efficiency video coding (HEVC)
- rate distortion optimization (RDO)
- video coding
ASJC Scopus subject areas
- Signal Processing
- Media Technology
- Computer Science Applications
- Electrical and Electronic Engineering
Cite this
Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. / Sun, Heming; Zhou, Dajiang; Hu, Landan; Kimura, Shinji; Goto, Satoshi.
In: IEEE Transactions on Multimedia, Vol. 19, No. 11, 7918540, 01.11.2017, p. 2375-2390.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC
AU - Sun, Heming
AU - Zhou, Dajiang
AU - Hu, Landan
AU - Kimura, Shinji
AU - Goto, Satoshi
PY - 2017/11/1
Y1 - 2017/11/1
N2 - In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra-and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the 'all-intra' configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.
AB - In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra-and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the 'all-intra' configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.
KW - Encoding
KW - high efficiency video coding (HEVC)
KW - rate distortion optimization (RDO)
KW - video coding
UR - http://www.scopus.com/inward/record.url?scp=85032209621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85032209621&partnerID=8YFLogxK
U2 - 10.1109/TMM.2017.2700629
DO - 10.1109/TMM.2017.2700629
M3 - Article
AN - SCOPUS:85032209621
VL - 19
SP - 2375
EP - 2390
JO - IEEE Transactions on Multimedia
JF - IEEE Transactions on Multimedia
SN - 1520-9210
IS - 11
M1 - 7918540
ER -