Fast SAO estimation algorithm and its VLSI architecture

Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

SAO estimation is the process of determining SAO parameters in video encoding. There are two difficulties for VLSI implementation of SAO estimation. The first is that there are huge amount of samples to deal with in statistic collection phase. The other is that the complexity of RDO in parameters determination phase is very high. In this article, a fast SAO estimation algorithm and its corresponding VLSI architecture are proposed. For the first difficulty, we use bitmaps to collect statistic of all the 16 samples in one 4×4 block simultaneously. For the second difficulty, we simplify a series of complicated procedures in HM to balance the complexity and BD-rate performance. Experimental results show that the proposed algorithm maintains the picture quality improvement. The VLSI design based on this algorithm can be implemented by 156.32K gates, 8832 bits SPRAM, 400MHz @ 65nm technology and is capable of 8Kx4K @ 120fps encoding.

Original languageEnglish
Title of host publication2014 IEEE International Conference on Image Processing, ICIP 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1278-1282
Number of pages5
ISBN (Print)9781479957514
DOIs
Publication statusPublished - 2014 Jan 28

Keywords

  • estimation
  • HEVC
  • SAO
  • VLSI

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

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    Zhu, J., Zhou, D., Kimura, S., & Goto, S. (2014). Fast SAO estimation algorithm and its VLSI architecture. In 2014 IEEE International Conference on Image Processing, ICIP 2014 (pp. 1278-1282). [7025255] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICIP.2014.7025255