FCSCAN

An efficient multiscan-based test compression technique for test cost reduction

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages653-658
Number of pages6
Volume2006
Publication statusPublished - 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama
Duration: 2006 Jan 242006 Jan 27

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CityYokohama
Period06/1/2406/1/27

Fingerprint

Cost reduction
Fans
Data compression
Product design
Costs
Hardware
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M., & Ohtsuki, T. (2006). FCSCAN: An efficient multiscan-based test compression technique for test cost reduction. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2006, pp. 653-658). [1594760]

FCSCAN : An efficient multiscan-based test compression technique for test cost reduction. / Shi, Youhua; Togawa, Nozomu; Kimura, Shinji; Yanagisawa, Masao; Ohtsuki, Tatsuo.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. p. 653-658 1594760.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shi, Y, Togawa, N, Kimura, S, Yanagisawa, M & Ohtsuki, T 2006, FCSCAN: An efficient multiscan-based test compression technique for test cost reduction. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2006, 1594760, pp. 653-658, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, 06/1/24.
Shi Y, Togawa N, Kimura S, Yanagisawa M, Ohtsuki T. FCSCAN: An efficient multiscan-based test compression technique for test cost reduction. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. 2006. p. 653-658. 1594760
Shi, Youhua ; Togawa, Nozomu ; Kimura, Shinji ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / FCSCAN : An efficient multiscan-based test compression technique for test cost reduction. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. pp. 653-658
@inproceedings{84b21c06e6d94b89a9aae48f658e52c7,
title = "FCSCAN: An efficient multiscan-based test compression technique for test cost reduction",
abstract = "This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.",
author = "Youhua Shi and Nozomu Togawa and Shinji Kimura and Masao Yanagisawa and Tatsuo Ohtsuki",
year = "2006",
language = "English",
isbn = "0780394518",
volume = "2006",
pages = "653--658",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - FCSCAN

T2 - An efficient multiscan-based test compression technique for test cost reduction

AU - Shi, Youhua

AU - Togawa, Nozomu

AU - Kimura, Shinji

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2006

Y1 - 2006

N2 - This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.

AB - This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.

UR - http://www.scopus.com/inward/record.url?scp=33748615132&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748615132&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0780394518

SN - 9780780394513

VL - 2006

SP - 653

EP - 658

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -