Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Shigenobu Maeda, Yoshiki Wada, Kazuya Yamamoto, Hiroshi Komurasaki, Takuji Matsumoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yasuo Yamaguchi, Takashi Ipposhi, Kimio Ueda, Koichiro Mashiko, Shigeto Maegawa, Masahide Inuishi

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A 0.18 μm cilicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.

Original languageEnglish
Pages (from-to)2065-2073
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume48
Issue number9
DOIs
Publication statusPublished - 2001 Sep
Externally publishedYes

Fingerprint

SOI (semiconductors)
isolation
CMOS
Metals
analogs
electrical resistivity
Substrates
MOSFET devices
Oxides
metal oxide semiconductors
field effect transistors
Noise figure
oxides
wireless communication
inductors
low noise
floating
linearity
Oxide semiconductors
Q factors

Keywords

  • Analog circuits
  • Inductors
  • Metal-oxide-semiconductor field-effect transistor (MOSFET)
  • Noise measurement
  • Silicon on insulator technology (SOI)
  • Wireless LAN

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications. / Maeda, Shigenobu; Wada, Yoshiki; Yamamoto, Kazuya; Komurasaki, Hiroshi; Matsumoto, Takuji; Hirano, Yuuichi; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Ipposhi, Takashi; Ueda, Kimio; Mashiko, Koichiro; Maegawa, Shigeto; Inuishi, Masahide.

In: IEEE Transactions on Electron Devices, Vol. 48, No. 9, 09.2001, p. 2065-2073.

Research output: Contribution to journalArticle

Maeda, S, Wada, Y, Yamamoto, K, Komurasaki, H, Matsumoto, T, Hirano, Y, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Ueda, K, Mashiko, K, Maegawa, S & Inuishi, M 2001, 'Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications', IEEE Transactions on Electron Devices, vol. 48, no. 9, pp. 2065-2073. https://doi.org/10.1109/16.944197
Maeda, Shigenobu ; Wada, Yoshiki ; Yamamoto, Kazuya ; Komurasaki, Hiroshi ; Matsumoto, Takuji ; Hirano, Yuuichi ; Iwamatsu, Toshiaki ; Yamaguchi, Yasuo ; Ipposhi, Takashi ; Ueda, Kimio ; Mashiko, Koichiro ; Maegawa, Shigeto ; Inuishi, Masahide. / Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications. In: IEEE Transactions on Electron Devices. 2001 ; Vol. 48, No. 9. pp. 2065-2073.
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