Filter router: An enhanced router design for efficient stacked shared cache network

Huatao Zhao, Xu Jia, Takahiro Watanabe

Research output: Contribution to journalLetter

1 Citation (Scopus)

Abstract

In this paper, many shared cache accesses such as crossed accesses and repeated accesses will be filtered in proposed router network for purpose of access latency reduction. Firstly, the distribution features of all shared cache accesses are analyzed for further optimization on access latency. And then, a meshed router network integrated with enhanced routers is proposed for fast identification of target accesses and further handling them. Hence, the experimental results show that our network design can achieve an average improvement of 26.1 percent on speedup IPC and an average saving of 9.7 percent on energy consumption over base system.

Original languageEnglish
Article number20190358
Journalieice electronics express
Volume16
Issue number14
DOIs
Publication statusPublished - 2019 Jan 1

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Keywords

  • Network on a chip
  • Router architecture
  • Shared cache memory
  • Stacked integration
  • TSVs

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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