FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. In this paper, we design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    Pages701-704
    Number of pages4
    DOIs
    Publication statusPublished - 2008
    EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao
    Duration: 2008 Nov 302008 Dec 3

    Other

    OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
    CityMacao
    Period08/11/3008/12/3

    Fingerprint

    FIR filters
    Engines
    Digital storage
    Specifications
    Processing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T., & Satoh, M. (2008). FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 701-704). [4746120] https://doi.org/10.1109/APCCAS.2008.4746120

    FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm. / Tamura, Ryo; Honma, Masayuki; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo; Satoh, Makoto.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. p. 701-704 4746120.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tamura, R, Honma, M, Togawa, N, Yanagisawa, M, Ohtsuki, T & Satoh, M 2008, FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 4746120, pp. 701-704, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 08/11/30. https://doi.org/10.1109/APCCAS.2008.4746120
    Tamura R, Honma M, Togawa N, Yanagisawa M, Ohtsuki T, Satoh M. FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. p. 701-704. 4746120 https://doi.org/10.1109/APCCAS.2008.4746120
    Tamura, Ryo ; Honma, Masayuki ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo ; Satoh, Makoto. / FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. pp. 701-704
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    abstract = "Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. In this paper, we design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching.",
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    AU - Ohtsuki, Tatsuo

    AU - Satoh, Makoto

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