Abstract
Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and buspacking are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010 |
| Pages | 632-637 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 11th International Symposium on Quality Electronic Design, ISQED 2010 - San Jose, CA Duration: 2010 Mar 22 → 2010 Mar 24 |
Other
| Other | 11th International Symposium on Quality Electronic Design, ISQED 2010 |
|---|---|
| City | San Jose, CA |
| Period | 10/3/22 → 10/3/24 |
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Keywords
- Bus planning
- Deterministic algorithm
- Fixed outline
- Floorplanning
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Fixed outline multi-bend bus driven floorplanning. / Sheng, Wenxu; Dong, Sheqin; Wu, Yuliang; Goto, Satoshi.
Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. 2010. p. 632-637 5450512.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Fixed outline multi-bend bus driven floorplanning
AU - Sheng, Wenxu
AU - Dong, Sheqin
AU - Wu, Yuliang
AU - Goto, Satoshi
PY - 2010
Y1 - 2010
N2 - Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and buspacking are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
AB - Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and buspacking are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
KW - Bus planning
KW - Deterministic algorithm
KW - Fixed outline
KW - Floorplanning
UR - http://www.scopus.com/inward/record.url?scp=77952617295&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952617295&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2010.5450512
DO - 10.1109/ISQED.2010.5450512
M3 - Conference contribution
AN - SCOPUS:77952617295
SN - 9781424464555
SP - 632
EP - 637
BT - Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
ER -