Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology

Sumio Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Group signature is one of the main theme in recent digital signature studies. Typical signature algorithm is a combination of more than 70 elliptic curve (ECC), modular (RSA), long-bit integer and hash arithmetic functions. A full H/W IP core is strongly desired for the use of group signature in SoCs in slow-clock and low-power mobile devices and embedded systems. Flexible adjustment of H/W speed and size, depending on different systems and LSI process technologies, is also required. However, for designing and verifying H/W, the group signature algorithm is too complicated to use a standard RTL (Register Transfer Level) design methodology nor any recent HLS (High Level Synthesis). Therefore, we incorporated a two-level behavioral synthesis approach, where an optimized macro-architecture is explored by a custom-made scheduler, after a database of multiple number of microarchitectures are effectively constructed by conventional HLS. We implemented the signature algorithm on a low-cost 0.25um gate-array. The H/W size is approximately 1M gates and our chip can compute a group signature at the equivalent speed (0.135 seconds@100MHz clock) with 3GHz PC S/W, while the power consumption is two orders of magnitude lower (425mW@100MHz).

Original languageEnglish
Title of host publication2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011
Pages57-62
Number of pages6
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011 - San Diego, CA, United States
Duration: 2011 Jun 52011 Jun 6

Publication series

Name2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011

Conference

Conference2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011
CountryUnited States
CitySan Diego, CA
Period11/6/511/6/6

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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    Morioka, S., Isshiki, T., Obana, S., Nakamura, Y., & Sako, K. (2011). Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. In 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011 (pp. 57-62). [5954996] (2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011). https://doi.org/10.1109/HST.2011.5954996