Floating body RAM technology and its scalability to 32nm node and beyond

Tomoaki Shino, Naoki Kusunoki, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, Atsushi Sakamoto, Jun Nishimura, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Abstract

Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the Floating Body Cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant.

Original languageEnglish
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
DOIs
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States
Duration: 2006 Dec 102006 Dec 13

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2006 International Electron Devices Meeting, IEDM
CountryUnited States
CitySan Francisco, CA
Period06/12/1006/12/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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