FLOOR-PLAN DESIGN SYSTEM FOR LSI LAYOUT.

Takahiro Watanabe, Hiroshi Baba

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

The authors have presented a floor-plan design system having two planning algorithms and facilities for editing design data and interactively improving floor-plan results. Though user requirements vary for different floor-plans, this system can edit any design data according to the requirements and meet the requirements quickly by presenting prototype floor-plans with evaluation. However, it is necessary not only to select a proper algorithm but also to define an appropriate connectivity. Several connectivities have been investigated to determine whether they could meet such demands or not. Connectivities depending on the Fibonacci number sequence appeared to be appropriate. The worst-case time complexities for practical-sized problems have been determined experimentally.

Original languageEnglish
Pages (from-to)9-12
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1985 Dec 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'FLOOR-PLAN DESIGN SYSTEM FOR LSI LAYOUT.'. Together they form a unique fingerprint.

  • Cite this