Floorplan-aware high-level synthesis for generalized distributed-register architectures

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    8 Citations (Scopus)

    Abstract

    As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

    Original languageEnglish
    Pages (from-to)3169-3179
    Number of pages11
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE92-A
    Issue number12
    DOIs
    Publication statusPublished - 2009 Dec

    Fingerprint

    High-level Synthesis
    Controllers
    Floorplanning
    Networks (circuits)
    Controller
    Interconnection
    Scheduling
    Unit
    Critical Path
    Signal Control
    Architecture
    High level synthesis
    Iteration
    Decrease
    Experimental Results

    Keywords

    • Distributed-register architecture
    • Floorplan
    • Generalized distributed-register architecture
    • High-level synthesis
    • Local controller
    • Local register

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    @article{61ea9691d69749aa85ff80b61e742ed7,
    title = "Floorplan-aware high-level synthesis for generalized distributed-register architectures",
    abstract = "As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7{\%} while maintaining the performance of the circuit equal with that using original distributed-register architectures.",
    keywords = "Distributed-register architecture, Floorplan, Generalized distributed-register architecture, High-level synthesis, Local controller, Local register",
    author = "Akira Ohchi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",
    year = "2009",
    month = "12",
    doi = "10.1587/transfun.E92.A.3169",
    language = "English",
    volume = "E92-A",
    pages = "3169--3179",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - Floorplan-aware high-level synthesis for generalized distributed-register architectures

    AU - Ohchi, Akira

    AU - Togawa, Nozomu

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 2009/12

    Y1 - 2009/12

    N2 - As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

    AB - As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

    KW - Distributed-register architecture

    KW - Floorplan

    KW - Generalized distributed-register architecture

    KW - High-level synthesis

    KW - Local controller

    KW - Local register

    UR - http://www.scopus.com/inward/record.url?scp=84864962353&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84864962353&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E92.A.3169

    DO - 10.1587/transfun.E92.A.3169

    M3 - Article

    AN - SCOPUS:84864962353

    VL - E92-A

    SP - 3169

    EP - 3179

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -