Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.

    Original languageEnglish
    Pages (from-to)2597-2611
    Number of pages15
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE96-A
    Issue number12
    DOIs
    Publication statusPublished - 2013

    Fingerprint

    High-level Synthesis
    Voltage
    Electric potential
    Floorplanning
    Energy Saving
    Leakage
    Interconnection
    Architecture
    High level synthesis
    Energy conservation
    Scheduling
    Integrate
    Iteration
    Module
    Unit
    Experimental Results
    Energy

    Keywords

    • Dynamic multiple supply voltages
    • Energy-optimization
    • High-level synthesis
    • Interconnection delay

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    @article{edaaf2996e724fc98fd8b2633e2faf3e,
    title = "Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages",
    abstract = "In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9{\%} energy-saving compared with conventional algorithms.",
    keywords = "Dynamic multiple supply voltages, Energy-optimization, High-level synthesis, Interconnection delay",
    author = "Abe, {Shin Ya} and Youhua Shi and Kimiyoshi Usami and Masao Yanagisawa and Nozomu Togawa",
    year = "2013",
    doi = "10.1587/transfun.E96.A.2597",
    language = "English",
    volume = "E96-A",
    pages = "2597--2611",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

    AU - Abe, Shin Ya

    AU - Shi, Youhua

    AU - Usami, Kimiyoshi

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2013

    Y1 - 2013

    N2 - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.

    AB - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture), which integrates dynamic multiple supply voltages and interconnection delay into high-level synthesis. In AVHDR architecture, voltages can be dynamically assigned for energy reduction. In other words, low supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Next, an AVHDR-based high-level synthesis algorithm is proposed. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, the modules in each huddle can be placed close to each other and the corresponding AVHDR architecture can be generated and optimized with floorplanning information. Experimental results show that on average our algorithm achieves 43.9% energy-saving compared with conventional algorithms.

    KW - Dynamic multiple supply voltages

    KW - Energy-optimization

    KW - High-level synthesis

    KW - Interconnection delay

    UR - http://www.scopus.com/inward/record.url?scp=84888992773&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84888992773&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E96.A.2597

    DO - 10.1587/transfun.E96.A.2597

    M3 - Article

    AN - SCOPUS:84888992773

    VL - E96-A

    SP - 2597

    EP - 2611

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -