Floorplan-driven high-level synthesis for distributed/shared-register architectures

Akira Ohchi*, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/ FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.

Original languageEnglish
Pages (from-to)78-90
Number of pages13
JournalIPSJ Transactions on System LSI Design Methodology
Publication statusPublished - 2008 Aug

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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