Floorplan-driven high-level synthesis for distributed/shared-register architectures

Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    8 Citations (Scopus)

    Abstract

    In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/ FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.2% while maintaining the performance of the circuit equal with that using distributed-register architectures.

    Original languageEnglish
    Pages (from-to)78-90
    Number of pages13
    JournalIPSJ Transactions on System LSI Design Methodology
    Volume1
    DOIs
    Publication statusPublished - 2008 Aug

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    Scheduling
    Networks (circuits)
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications

    Cite this

    Floorplan-driven high-level synthesis for distributed/shared-register architectures. / Ohchi, Akira; Kohara, Shunitsu; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    In: IPSJ Transactions on System LSI Design Methodology, Vol. 1, 08.2008, p. 78-90.

    Research output: Contribution to journalArticle

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