Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper, we propose a floorplan-driven highlevel synthesis algorithm utilizing both volatile and non-volatile registers for hybrid energy-harvesting systems. In our algorithm, we firstly introduce an idea of safety line candidates. Based on them, we perform safety-line (SL) scheduling so that every operation does not cross the safety line candidates and then perform volatile/non-volatile register binding so that all the data crossing the safety line candidates are stored into non-violate registers. We can safely restore all the data and re-start the circuit operation from every safety line candidate, even if the power shut-off occurs while running the circuit. Experimental results show that our algorithm reduces average latency by 30.76% and the average energy consumption by 24.94% compared to the naive algorithm when sufficient energy is given (normal mode). Experimental results also show that our algorithm reduces average latency by 30.58% compared to the naive algorithm by reducing rollback execution if a small amount of energy is given (energy-harvesting mode).

    Original languageEnglish
    Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
    PublisherIEEE Computer Society
    Pages64-67
    Number of pages4
    Volume2017-October
    ISBN (Electronic)9781509066247
    DOIs
    Publication statusPublished - 2018 Jan 8
    Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
    Duration: 2017 Oct 252017 Oct 28

    Other

    Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
    CountryChina
    CityGuiyang
    Period17/10/2517/10/28

    Fingerprint

    Energy harvesting
    Networks (circuits)
    High level synthesis
    Energy utilization
    Scheduling

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Asai, D., Yanagisawa, M., & Togawa, N. (2018). Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 64-67). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252412

    Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. / Asai, Daiki; Yanagisawa, Masao; Togawa, Nozomu.

    Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. p. 64-67.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Asai, D, Yanagisawa, M & Togawa, N 2018, Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. in Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. vol. 2017-October, IEEE Computer Society, pp. 64-67, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 17/10/25. https://doi.org/10.1109/ASICON.2017.8252412
    Asai D, Yanagisawa M, Togawa N. Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October. IEEE Computer Society. 2018. p. 64-67 https://doi.org/10.1109/ASICON.2017.8252412
    Asai, Daiki ; Yanagisawa, Masao ; Togawa, Nozomu. / Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. pp. 64-67
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