Floorplanning and topology generation for application-specific network-on-chip

Bei Yu, Sheqin Dong, Song Chen, Satoshino Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Citations (Scopus)

Abstract

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages535-540
Number of pages6
DOIs
Publication statusPublished - 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei
Duration: 2010 Jan 182010 Jan 21

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CityTaipei
Period10/1/1810/1/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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  • Cite this

    Yu, B., Dong, S., Chen, S., & Goto, S. (2010). Floorplanning and topology generation for application-specific network-on-chip. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 535-540). [5419825] https://doi.org/10.1109/ASPDAC.2010.5419825