Floorplanning driven network-on-chip synthesis for 3-D SoCs

Wei Zhong*, Song Chen, Fei Ma, Takeshi Yoshimura, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)


1 As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network-on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Number of pages4
Publication statusPublished - 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro
Duration: 2011 May 152011 May 18


Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CityRio de Janeiro

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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