Floorplanning driven network-on-chip synthesis for 3-D SoCs

Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

1 As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network-on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1203-1206
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro
Duration: 2011 May 152011 May 18

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CityRio de Janeiro
Period11/5/1511/5/18

Fingerprint

Switches
Silicon
Linear programming
Interfaces (computer)
Electric power utilization
Topology
Network-on-chip
System-on-chip
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zhong, W., Chen, S., Ma, F., Yoshimura, T., & Goto, S. (2011). Floorplanning driven network-on-chip synthesis for 3-D SoCs. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1203-1206). [5937785] https://doi.org/10.1109/ISCAS.2011.5937785

Floorplanning driven network-on-chip synthesis for 3-D SoCs. / Zhong, Wei; Chen, Song; Ma, Fei; Yoshimura, Takeshi; Goto, Satoshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2011. p. 1203-1206 5937785.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhong, W, Chen, S, Ma, F, Yoshimura, T & Goto, S 2011, Floorplanning driven network-on-chip synthesis for 3-D SoCs. in Proceedings - IEEE International Symposium on Circuits and Systems., 5937785, pp. 1203-1206, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, 11/5/15. https://doi.org/10.1109/ISCAS.2011.5937785
Zhong W, Chen S, Ma F, Yoshimura T, Goto S. Floorplanning driven network-on-chip synthesis for 3-D SoCs. In Proceedings - IEEE International Symposium on Circuits and Systems. 2011. p. 1203-1206. 5937785 https://doi.org/10.1109/ISCAS.2011.5937785
Zhong, Wei ; Chen, Song ; Ma, Fei ; Yoshimura, Takeshi ; Goto, Satoshi. / Floorplanning driven network-on-chip synthesis for 3-D SoCs. Proceedings - IEEE International Symposium on Circuits and Systems. 2011. pp. 1203-1206
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