Floorplanning for high utilization of heterogeneous FPGAs

Nan Liu, Song Chen, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and ram blocks (RAMs) where millions of logic gates (a growing trend to implement larger and more complex functions) included have been added to field programmable gate arrays (FPGAs). And floorplanning for this, hierarchical approach is recognized as the most effective method. The FPGA architecture shows that CLBs hold the maximum quantity much more than other resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. The proposed method can make the resource requirement of functional modules satisfied with a high resource utilization. First, we use a non-slicing floorplanning method to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, such that all the functional modules get CLB requirements satisfied. Finally, the MULs and RAMs are allocated to modules by a network flow model. The results show that about 7%-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages270-275
Number of pages6
DOIs
Publication statusPublished - 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA
Duration: 2011 Mar 142011 Mar 16

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CitySanta Clara, CA
Period11/3/1411/3/16

Fingerprint

Field programmable gate arrays (FPGA)
Random access storage
Logic gates
Costs

Keywords

  • Floorplanning
  • heterogeneous field programmable gate arrays
  • high utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Liu, N., Chen, S., & Yoshimura, T. (2011). Floorplanning for high utilization of heterogeneous FPGAs. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 270-275). [5770736] https://doi.org/10.1109/ISQED.2011.5770736

Floorplanning for high utilization of heterogeneous FPGAs. / Liu, Nan; Chen, Song; Yoshimura, Takeshi.

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. p. 270-275 5770736.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, N, Chen, S & Yoshimura, T 2011, Floorplanning for high utilization of heterogeneous FPGAs. in Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011., 5770736, pp. 270-275, 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, CA, 11/3/14. https://doi.org/10.1109/ISQED.2011.5770736
Liu N, Chen S, Yoshimura T. Floorplanning for high utilization of heterogeneous FPGAs. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. p. 270-275. 5770736 https://doi.org/10.1109/ISQED.2011.5770736
Liu, Nan ; Chen, Song ; Yoshimura, Takeshi. / Floorplanning for high utilization of heterogeneous FPGAs. Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. pp. 270-275
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