Floorplanning using a tree representation

Pei Ning Guo, Toshihiko Takahashi, Chung Kuan Cheng, Takeshi Yoshimura

Research output: Contribution to journal › Article

70 Citations (Scopus)

Abstract

We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only n(2 + [lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!22n-2/n1.5). This is very concise compared to a sequence pair representation that has O((n!)2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n2(n/4e)n). The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!25n-3/n1.5) combinations. Given an O tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method.

Original languageEnglish
Pages (from-to)281-289
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume20
Issue number2
DOIs
Publication statusPublished - 2001 Feb
Externally publishedYes

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Binary trees
Program processors
Wire

Keywords

  • Building block placement
  • Floorplan
  • Rooted ordered tree

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Floorplanning using a tree representation. / Guo, Pei Ning; Takahashi, Toshihiko; Cheng, Chung Kuan; Yoshimura, Takeshi.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 2, 02.2001, p. 281-289.

Research output: Contribution to journal › Article

Guo, PN, Takahashi, T, Cheng, CK & Yoshimura, T 2001, 'Floorplanning using a tree representation', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 281-289. https://doi.org/10.1109/43.908471
Guo PN, Takahashi T, Cheng CK, Yoshimura T. Floorplanning using a tree representation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2001 Feb;20(2):281-289. https://doi.org/10.1109/43.908471
Guo, Pei Ning ; Takahashi, Toshihiko ; Cheng, Chung Kuan ; Yoshimura, Takeshi. / Floorplanning using a tree representation. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2001 ; Vol. 20, No. 2. pp. 281-289.
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